CMOS RF integrated circuits at 5 GHz and beyond

A strong demand for wireless products, an insatiable thirst for spectrum th at pushed carrier frequencies ever upward, and the constant quest for highe r performance at lowe power and cost, have recently driven the development of radio frequency integrated circuit (RFIC) technology in unprecedented wa ys. These pressures are stimulating novel solutions that allow RFICs to enj oy more of the benefits of Moore's law than has been the case in the past. In addition to regular raw transistor speed increased, the growing number o f interconnect layers allows the realization of improved inductors, capacit ors, and transmission lines. A deeper understanding of noise at both the de vice and circuit level has improved the performance of low noise amplifiers (LNAs) and oscillators. Finally, an appropriate raiding of circuit ideas d ating back to the vacuum tube era enables excellent performance, even when working close to the limits of a technology. This paper surveys some of these developments in the context of low-power R F CMOS technology, with a focus on an illustrative implementation of a low- power 5-GHz wireless LAN receiver in 0.25-mum CMOS. Thanks to these recent advances in passive components and active circuits, the blocks comprising t he receiver consume a total of approximately 37 mW. These blocks include an image-reject LNA, image-reject downconverter, and a complete frequency syn thesizer. The overall noise figure is 5 dB, and the input-referred third-or der intercept (IIP3) is -2 dBNM. To underscore that 5 GHz does not represen t an upper bound by any means, this paper concludes with a look at active c ircuits that function beyond 15-20 GHz, and a characterization of on-chip t ransmission lines up to 50 GHz, all in the context of how scaling is expect ed to share future developments.