MOSFET scaling into the 10 nm regime

Scaling limits of the double-gate MOSFET structure are explored. Because sh ort-channel effects can be adequately controlled by thinning the silicon bo dy, the eventual scaling limit will be determined by the ability to control off-state leakage due to quantum mechanical tunneling and thermionic emiss ion between the source and drain. Depending on threshold voltage and the so urce/drain doping profile, this will restrict gate length scaling to 5-11 n m. As power supplies are scaled down, maintaining on-state drive current ma y become difficult due to threshold voltage limitations. Series resistance becomes important as the body thickness is reduced, but intrinsic device pe rformance may still be improved. (C) 2000 Academic Press.