Design of a 3.3-v 1-GHz CMOS phase locked loop with a two-stage self-feedback ring oscillator

A 3.3-V PLL (phase locked loop) is designed for high-frequency, low-voltage , and low-power applications. This paper proposes a new PLL architecture to improve the voltage-to-frequency linearity of a VCO (voltage controlled os cillator) with a new delay cell. The proposed VCO operates in a wide freque ncy range of 30 MHz similar to1 GHz, with good linearity. The DC-DC voltage up/down converter is newly designed to regulate the control Voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6-mum n -well CMOS process. The simulation results show a locking time of 2.6 sec a t 1 GHz, a lock in range of 100 MHz similar to1 GHz, and a power dissipatio n of 112 mW.