VLSI architecture for fast motion estimation based on bit-plane matching

In this paper, we propose a VLSI (very large scale integrated circuit) arch itecture for fast motion estimation based on bit-plane matching. The propos ed architecture performs binary motion estimation by using a 1-bit plane im age of the video sequence. The proposed motion estimator can be implemented using only simple Boolean functions, which can greatly reduce the hardware cost and the time overhead. Furthermore. the proposed architecture employs a pair of processing cores that calculate the motion vector continuously. By controlling the data flow in a systolic fashion using internal shift reg isters in the processing cores, we avoid using SRAM (local memory) so that we remove the time overhead for accessing the local memory and can exploit lower-cost fabrication technology The proposed system was designed to proce ss reference blocks of size 16 x 16 and the search range of [-16, 15]. We m odeled and tested the proposed motion estimator in VHDL (very high speed in tegrated circuit hardware description language) and then synthesized the wh ole system which has been integrated in a 0.6-mum triple-metal CMOS chip of size 8.15 x 10.84 mm(2).