Low-power flip-flops with reliable clock gating

The paper presents two gated flip-flops aimed at low-power applications. Th e proposed hip-hops use new gating techniques that reduce power dissipation deactivating the clock signal. The presented circuits overcome the clock d uty-cycle limitation of previously reported gated flip-flops. Circuit simulations with the inclusion of parasitics show that sensible pow er dissipation reduction is possible if the input signal has reduced switch ing activity. A 16-bit counter and an audio sampler register are presented as examples of low-power applications. (C) 2000 Elsevier Science Ltd. All r ights reserved.