Device simulation of a n-DMOS cell with trench isolation

Authors
Kamoulakos, G Haniotakis, T Tsiatouhas, Y Schoellkopf, JP Arapoyanni, A
Citation
G. Kamoulakos et al., Device simulation of a n-DMOS cell with trench isolation, MICROELEC J, 32(1), 2001, pp. 75-80
Citations number
9
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
MICROELECTRONICS JOURNAL
ISSN journal
00262692 → ACNP
Volume
32
Issue
1
Year of publication
2001
Pages
75 - 80
Database
ISI
SICI code
0026-2692(200101)32:1<75:DSOANC>2.0.ZU;2-J
Abstract
The DMOS cell, a high-voltage transistor, implemented in low voltage standa rd 0.18 mum double-well CMOS technology with trench isolation is studied. T he operation of the cell is investigated with the use of a device simulator while the effect of the trench to the operation of the cell is revealed. ( C) 2000 Elsevier Science Ltd. All rights reserved.