AN ADIABATIC QUATERNARY LOGIC-CIRCUIT

Multiple-valued logic has been proposed as a means for reducing the po wer, improving the speed, and increasing the packing density of VLSI c ircuits. Low-energy (adiabatic) logic circuits have also been proposed to reduce energy consumption of VLSI logic functions. Instead of the conventional DC power supply, these adiabatic logic circuits use 'AC' power supplies (power clocks) that allow energy recovery and also serv e as timing clocks for the logic. In this paper we describe the adiaba tic operation of a quaternary logic circuit.