Citation
N. Kranitis et al., Power-/energy-efficient BIST schemes for processor data paths, IEEE DES T, 17(4), 2000, pp. 15-28
Citations number
18
Categorie Soggetti
Computer Science & Engineering
Journal title
IEEE DESIGN & TEST OF COMPUTERS
ISSN journal
07407475
→ ACNP
Volume
17
Issue
4
Year of publication
2000
Pages
15 - 28
Database
ISI
SICI code
0740-7475(200010/12)17:4<15:PBSFPD>2.0.ZU;2-2
Abstract
Processor core power is primarily consumed in a data path consisting of hig
h-activity functional modules. We propose low-power/energy BIST schemes for
data path architectures built around the most common combinations of multi
pliers, adders, ALUs, and shifters.