A dual-mode 700-MSamples/s 6-bit 200-MSamples/s 7-bit A/D converter in a 0.25-mu m digital CMOS process

Citation
K. Nagaraj et al., A dual-mode 700-MSamples/s 6-bit 200-MSamples/s 7-bit A/D converter in a 0.25-mu m digital CMOS process, IEEE J SOLI, 35(12), 2000, pp. 1760-1768
Citations number
15
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
ISSN journal
00189200 → ACNP
Volume
35
Issue
12
Year of publication
2000
Pages
1760 - 1768
Database
ISI
SICI code
0018-9200(200012)35:12<1760:AD7627>2.0.ZU;2-2
Abstract
The design of a high-speed analog-to-digital (A/D) converter for hard disk drive read channels is described, The A/D converter uses a flash architectu re with an interleaved sample and hold and interpolating comparator pre-amp lifiers, It has 6 bits of resolution at full speed as well as a 7-bit mode operating at a lower speed. The 7-bit mode is useful for servo signal proce ssing, This AID converter has been implemented in a four-level metal single -poly 0.25-mum CMOS technology. The device operates at a speed of up to 700 MSamples/s in the 6-bit mode while maintaining an signal-to-noise-plus-dis tortion rate (SNDR) of greater than 35 dB at input frequencies of up to one -fourth the sampling rate, In the 7-bit mode, the device operates at up to 200 MSamples/s with a SNDR greater than 41 dB, It occupies an active area o f 0.45 mm(2) and consumes less than 187 mW of power.