A 3.3-V 12-b 50-MS/s A/D converter in 0.6-mu m CMOS with over 80-dB SFDR

A 12-b analog-to-digital converter (ADC) is optimized for spurious-free dyn amic range (SFDR) performance at low supply voltage and suitable for use in modern wireless base stations. The 6-7-b two-stage pipeline ADC uses a boo tstrap circuit to linearize the sampling switch of an on-chip sample-and-ho ld (SIH) and achieves over 80-dB SFDR for signal frequencies up to 75 MHz a t 50 MSample/s (MSPS) without trimming, calibration, or dithering. INL is 1 .3 LSB, differential nonlinearity (DNL) is 0.8 LSB, The 6-h and 7-b flash s ub-ADCs are implemented efficiently using offset averaging and analog foldi ng. In 0.6-mum CMOS, the 16-mm(2) ADC dissipates 850 mW.