A three-stage bandpass sigma-delta (Sigma Delta) analog-to-digital converte
r has been designed specifically for operation at low oversampling ratios.
In the proposed architecture, the center frequency of the third stage is sh
ifted slightly from that of the first two stages to achieve more efficient
noise shaping across the signal band. An experimental modulator based on th
e proposed topology has been integrated in a 0.25-mum CMOS technology and a
chieves a dynamic range of 75 dB with a maximum signal-to-noise-plus-distor
tion ratio (SNDR) of 70 dB when digitizing a 2-MHz signal band centered at
16 MHz. This circuit implements an f(s)/4 bandpass architecture and thus op
erates at 64-MHz clock rate. It dissipates 110 mW from a 2.5-V supply, and
its active area is 4 mm(2).