A high-performance multibit Delta Sigma CMOS ADC

The design of a multibit Delta Sigma converter is presented. It uses a thir d-order 4-bit Delta Sigma topology with data weighted averaging (DWA) to re duce the linearity requirements of the digital-to-analog converters in the feedback loop. The implementation of the DWA algorithm is optimized to mini mize the delay introduced in the feedback loop, resulting in clock frequenc ies up to 100 MHz. Behavioral models are used to determine several building block specificatio ns. An accurate model is used to analyze the combined effect of the dominan t closed loop pole of the operational transconductance amplifier (OTA), the slew rate and the nonzero switch resistance. It is shown that the offset r equirements for the quantizer result in a large input capacitance of the qu antizer, Therefore scaling of the OTAs, as classically employed in single-b it PI: converters, tan no longer be used. For an oversampling ratio of only 24, the converter achieves a signal-to-no ise ratio of 95 dB, a signal-to-noise-plus-distortion ratio of 89 dB and an input dynamic range of 97 dB after comb-filtering. The converter is sample d at 60 MHz, resulting in a 2.5 MS/s output rate. It is implemented in a st andard 0.65-mum CMOS technology, occupies 5.3 mm(2) and consumes 295 mW fro m a 5-V power supply. When clocked at 100 MHz with an oversampling ratio of 8, a 12-bit resolution is achieved at an output rate of 12.5 MS/s.