A CMOS nested-chopper instrumentation amplifier with 100-nV offset

Authors
Bakker, A Thiele, K Huijsing, JH
Citation
A. Bakker et al., A CMOS nested-chopper instrumentation amplifier with 100-nV offset, IEEE J SOLI, 35(12), 2000, pp. 1877-1883
Citations number
10
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
ISSN journal
00189200 → ACNP
Volume
35
Issue
12
Year of publication
2000
Pages
1877 - 1883
Database
ISI
SICI code
0018-9200(200012)35:12<1877:ACNIAW>2.0.ZU;2-7
Abstract
A CMOS nested-chopper instrumentation amplifier is presented with a typical offset of 100 nV. This performance is obtained by nesting an additional lo w-frequency chopper pair around a conventional chopper amplifier. The inner chopper pair removes the 1/f noise, while the outer chopper pair reduces t he residual offset. The test chip is free from 1/f noise and has a thermal noise of 27 nV/root Hz consuming a total supply current of 200 muA.