A high IIP2 downconversion mixer using dynamic matching

This paper presents an RF downconversion mixer with improved rejection to s econd-order intermodulation for application within a direct-conversion rece iver requiring high blocking performance. The mixer, implemented in a 2.7-V 0.35-mum BiCMOS process, achieves a second-order input intercept point of at least +72 dBm for a BiCMOS design and at least +66 dBm for an all-CMOS d esign. The design utilizes dynamic matching to enhance the balance of a ful ly differential mixer through mitigation of both component and device misma tches. In addition, dynamic matching is shown to improve the mixer's 1/f no ise performance. For an all-CMOS mixer design, a 30-dB improvement in the m ixer's noise floor at 1 kHz has been observed compared to conventional full y differential CMOS Gilbert-cell mixer. Additionally, background is given o n second-order intermodulation and on system IIP2 requirements for a direct -conversion receiver.