A 0.6-W 10-Gb/s SONET/SDH fit-error-rate monitoring LSI

Authors
Kawai, K Ichino, H
Citation
K. Kawai et H. Ichino, A 0.6-W 10-Gb/s SONET/SDH fit-error-rate monitoring LSI, IEEE J SOLI, 35(12), 2000, pp. 1988-1991
Citations number
5
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
ISSN journal
00189200 → ACNP
Volume
35
Issue
12
Year of publication
2000
Pages
1988 - 1991
Database
ISI
SICI code
0018-9200(200012)35:12<1988:A01SFM>2.0.ZU;2-I
Abstract
A 10-Gbis SONET/SDH bit-error-rate monitoring LSI is fabricated by Si bipol ar process. A byte-aligning demur architecture based on tree-type demur and clock inversions by detecting inversion indicating patterns reduces the po wer to only 14% of that of the previous chip, The LSI dissipates 0.6 W with -3.3-V supply voltage.