Front-end readout system for PHENIX RICH

A front-end readout system with a custom backplane and custom circuit modul es has been developed for the RICH subsystem of the PHENIX experiment. The design specifications and test results of the backplane and the modules are presented in this paper. In the module design, flexibility for modificatio n is maximized through the use of Complex Programmable Logic Devices. In th e backplane design, a source-synchronous bus architecture is adopted for th e data and control bus. The transfer speed of the backplane has reached 640 Mbyte/s with a 128-bit data bus. Total transaction time is estimated to be less than 30 mus per event when this system is used in the experiment. Thi s result indicates that the performance satisfies the data-rate requirement of the PHENIX experiment. (C) 2000 Elsevier Science B.V. All rights reserv ed.