Investigation of candidate VRM topologies for future microprocessors

By reducing the power supply voltage, faster, lower power consumption, and high integration density data processing systems can be achieved. The curre nt generation high-speed complementary metal-oxide-semiconductor (CMOS) pro cessors (e.g., Alpha, Pentium, Power PC) are operating at above 300 MHz wit h 2.5 to 3.3 V output range. Future processors will be designed in the 1.1- 1.8 V range, to further enhance their speed-power performance, These new ge nerations microprocessors will present very dynamic loads with high current slew rates during transient. As a result, they will require a special powe r supply, voltage regulator module (VRM), to provide well-regulated voltage , The VRMs should have high power densities, high efficiencies, and good tr ansient performance. In this paper, the critical technical issues to achiev e this target for future generation microprocessors are addressed, And a VR M candidate topology, interleaved quasisquare-wave (QSW), is proposed. The design, simulation, and experimental results are presented.