Architecture and performance evaluation of a new functional memory: Functional memory for addition

Authors
Kobayashi, K Yamaoka, M Kobayashi, Y Onodera, H Tamaru, K
Citation
K. Kobayashi et al., Architecture and performance evaluation of a new functional memory: Functional memory for addition, IEICE T FUN, E83A(12), 2000, pp. 2400-2408
Citations number
10
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
ISSN journal
09168508 → ACNP
Volume
E83A
Issue
12
Year of publication
2000
Pages
2400 - 2408
Database
ISI
SICI code
0916-8508(200012)E83A:12<2400:AAPEOA>2.0.ZU;2-K
Abstract
We propose a functional memory for addition (FMA), which is a memory-merged logic LSI. It is a memory as well as a SIR ID parallel processor. To minim ize the area, a precessing element (PE) consists of several DRAM words and a bit-serial ALU. The ALU has a functionality of addition bit by bit. This paper describes two FR IA experimental LSIs. One is for general purpose, an d the other is for full search block matching of image compression. We esti mate that a 0.18 mum process realizes 57.000 PEs in a 50 mm(2) die, achievi ng 205 GOPS under 1.36 W power.