Dynamic fast issue (DFI) mechanism for dynamic scheduled processors

Superscalar processors can achieve increased performance by issuing instruc tions Out-of-Order (OoO) from the original instruction stream. Implementing an OoO instruction scheme requires a hardware mechanism to prevent incorre ctly executed instructions from updating registers values, In addition, per formance decreases if data dependencies, a branch or a trap among instructi ons appears. To this end ww propose a new mechanism named Dynamic Fast issu e (DFI) mechanism to issue instructions ill all OoO fashion to multiple par allel functional units without considerable hardware complexity. The above system, which will be implemented in our Superscalar Functional Assignments Register Microprocessor (FARM) [1], solves data dependencies, supports pre cise interrupt and branch prediction, which are the main problems associate d with the dynamic scheduling of instructions ill superscalar machines, Res ults are written only once, Write-once, directly; into the register file (R F). To ensure that results are written in order in their appropriate output registers, a record of instruction order and state is maintained by a stat us buffer (STB). A 64 entries integrated register file is implemented to ho ld both renamed and logical registers. To recover the processor state from an interrupt or a branch miss-prediction, a status buffer (STB) and a recov ery list table (RLT) are implemented. Novel aspects of the above system arc hitecture as well as the principle underlying: this process and the constra ints that must be met is presented, Performance evaluation results are perf ormed through full-pipelined-level architectural simulator and SPECint95 be nchmark programs.