A new method for constructing IP level power model based on power sensitivity

As the function uf a system getting more complex. IP (Intellectual Property ) reusing is the trend of system design style. Designers need to evaluate t he performance and features of every candidate IP block that can be used in their design, while IP providers hope to keep the structure of tilt ir IP blocks a secret. An IP level power model is a model that takes only the pri mary) input statistics its parameters and does not reveal any information a bout the sizes of the transistors or the structure of the circuit. This pap er proposes a new method for constructing power model that is suitable for IP level circuit blocks. It is a nominal point selection method, fur power models based oil power sensitivities. BS analyzing the relationship between the dynamic power consumption uf CMOS circuits and their input signal stat istics, a guideline of selecting the nominal point is proposed. From our an alysis. the first nominal point is selected to minimize the average Estimat ion error and two other nominal points are selected to minimize the maximum estimation error. Our experimental results on a number of benchmark circui ts show the effectiveness of the proposed method. Average estimation accura cy within 5.78% of transistor level simulations is achieved. The proposed m ethod can he applied to build a system level power estimation environment w ithout revealing the contents of the IP blocks inside. Thereby. it is a pro mising method for IP level power model construction.