Delay-optimal technology mapping for hard-wired non-homogeneous FPGAs

A delay-optimal technology mapping algorithm is developed on a general mode l of FPGA with hard-wired nonhomogeneous logic block architectures which is composed of different sizes of look-up tables (LUTs) hard-wired together. This architecture has the advantages of short delay of hard-wired connectio ns and area-efficiency of nun-homogeneous structure. The Xilinx XC4000 is o ne commercial example, where two 4-LUTs are hard-wired to one 3-LUT. In thi s paper, we present a two-dimensional labeling approach and a level-2 node cut algorithm to handle the hard-wired feature. The experimental results sh ow that our algorithm generates Favorable results for Xilinx XC4000 CLBs, O ver a set of MCNC benchmarks. our algorithm produces results with 17% fewer CLB depth than that of FlowMap in similar CPU time on average, and with 4% fewer CLB depth than that of PDDMAP on average while PDDMAP needs 15 times more CPU time.