Clock schedule design for minimum realization cost

A semi-synchronous circuit is a circuit ill which the clock is assumed tu b e distributed periodically to each individual register, though not necessar ily to all registers simultaneously. In this paper, we propose atl algorith m to achieve the target clock period by modifying a given target clock sche dule as small as possible, where the realization cost of the target clock s chedule is assumed to be minimum. The proposed algorithm iteratively improv es a feasible clock schedule. The algorithm finds a set of registers that c an reduce the cost by changing their clock timings with same amount, and ch anges the clock timing with optimal amount. Experiments show that the algor ithm achieves the target clock period with fewer modifications.