High level analysis of clock regions in a C++ system description

Timing verification of digital synchronous de signs is a complex process th at is traditionally carried out deep in the design cycle, at the gate level . A method, embodied in a C++ based design system. is presented that allows modeling and verification of clock regions at a higher level. By combining event-driven, clock-cycle true and behavioral simulation, Me are able to p erform static and dynamic timing analysis of the clock regions.