Alignment mark optimization to reduce tool- and wafer-induced shift for XRA-1000

As semiconductor device geometry shrinks down to the 100 nm order for the m ost critical layers, requirements for overlay accuracy have become increasi ngly strict in the semiconductor manufacturing process; One contribution to overlay error (particularly alignment error) originates from the process a nd tool interaction. Therefore, it is necessary to improve the alignment ac curacy of both the process and the tool. Alignment errors can be separated into tool-induced shift (TIS): wafer-induced shift (WIS), and TIS-WIS inter action. In this study, optimization of the alignment mark will be proposed in order to reduce not only TIS, but also WIS for the XRA-1000, which is th e volume production stepper of proximity X-ray lithography (PXL).