Optimization of sample plan for overlay and alignment accuracy improvement

The overlay control requirement for a sub-0.15 mum design rule device is no minally less than 40 nm. To meet this demand, every factor known to affect the overlay budget should be analyzed in detail and corrected as much as po ssible. One of the major causes degrading the overlay budget is the nonopti mized wafer sample plan. Compensated but undercorrected overlay errors fitt ed as linear terms can be amplified in case of using improper sample plan ( e.g., an asymmetric plan). In this study we investigated the sample plan de pendency of global alignment repeatability and overlay measurement accuracy . The achievement of better alignment repeatability is critical for improvi ng not only in-wafer overlay but wafer-to-wafer overlay control. Global ali gnment repeatability and its results are significantly affected by which ch ips in a wafer map are selected for global alignment use. Several sample pl ans which are limited to the symmetric group (i.e., translation, inversion, rotation and symmetric), are tested. The criteria for selecting the optimu m sample plan were the residuals and linear-term reproducibility, both of w hich are significantly affected by raw data noise. Raw data variations incl ude stage positioning errors and process-induced alignment signal abnormali ty. From among the candidates, we determined an optimal sample plan which l eaves the least residuals and exhibits repeatability as good as that in ful l chip measurement. Similar: results could be obtained for an overlay sampl e plan.