Voltage contrast defect inspection of contacts and vias for deep quarter micron devices

Electron beam induced voltage contrast of vias and contacts was investigate d for voltage contrast defect inspection. The investigation was carried out on the basis of signal intensity analysis of the voltage contrast image in relation to wafer bias and charge density of the incident electron beam. I t was determined that voltage contrast is dependent on the balance between the surface potential of the oxide surface due to charge-up and the surface potential of vias and contacts. By adjusting the parameters of the charge density and the wafer bias, the optimum conditions can be obtained. Using t his technique, the inspection of a 0.25 mum logic and 0.18 mum dynamic rand om access memory (DRAM) production wafer was carried out. The potential for inspecting electric anomalous failures of a 0.18-mum-design-rule device, w hich are difficult to detect by conventional optical inspection tools, was confirmed.