Dynamically scheduling VLIW instructions

Very long instruction word (VLIW) machines potentially provide the most dir ect way to exploit instruction-level parallelism; however, they cannot be u sed to emulate current general-purpose instruction set architectures. In ad dition, programs scheduled for a particular implementation of a VLIW model cannot be guaranteed to be binary compatible with other implementations of the same machine model with a different number of functional units or funct ional units with different latencies. This paper describes-an architecture, named dynamically trace scheduled VLIW (DTSVLIW), that can be used to impl ement machines that execute code of current RISC or CISC instruction set ar chitectures in a VLIW fashion, with backward code compatibility. Preliminar y measurements of the DTSVLIW performance, obtained with an execution-drive n simulator running the SPECint95 benchmark suite, are also presented. (C) 2000 Academic Press.