Electroless copper deposition for ultralarge-scale integration

Citation
Hh. Hsu et al., Electroless copper deposition for ultralarge-scale integration, J ELCHEM SO, 148(1), 2001, pp. C47-C53
Citations number
33
Categorie Soggetti
Physical Chemistry/Chemical Physics","Material Science & Engineering
Journal title
JOURNAL OF THE ELECTROCHEMICAL SOCIETY
ISSN journal
00134651 → ACNP
Volume
148
Issue
1
Year of publication
2001
Pages
C47 - C53
Database
ISI
SICI code
0013-4651(200101)148:1<C47:ECDFUI>2.0.ZU;2-0
Abstract
The characteristics of electroless copper plating on different substrates o f TiN/SiO2/Si, Cu-seed/Ta/SiO2/Si, and Cu-seed/TaN/SiO2/Si have been invest igated. Continuous copper films with good surface morphology are obtained, and hydrogen-induced blister formation is inhibited by optimizing plating s olution and conditions. Surface roughness of the electrolessly plated coppe r films increases with increasing film thickness, and the average roughness is 11 nm at a film thickness of 1 mum on Cu-seed/TaN/SiO2/Si substrate. Co nformal copper deposition with excellent step coverage completely fills dee p subquarter-micrometer features of high aspect ratios up to five. Copper g rowth orientation depends on the underlayer structure. A copper film with s trong (111) texture is plated on the (111) textured copper seed layer of Cu -seed/TaN/SiO2/Si substrate, while no preferred orientation is found on the other substrates. After thermal annealing at 400 degreesC in N-2/H-2 for 1 h, Cu(111) texture is enhanced in all systems. By thermal annealing, defec ts in the plated copper are reduced. and the electrical resistivity of the plated copper is lowered to 1.75 mu Ohm cm at room temperature. (C) 2000 Th e Electrochemical Society. All rights reserved.