Number shortening algorithms

This manuscript investigates a fundamental computational process-the shorte ning of floating point mantissas. One particularly surprising and useful re sult is the proof that a special version of bias removal (which can be exec uted with the swiftness of chopping) yields virtually the same error as doe s the symmetric rounding used in the IEEE floating point standards. This su ggests that the execution speed of current floating point chips could be in creased without detriment to their error behavior. Shortening errors are an alyzed both stochastically and by bounds. A comparison of worst-case versus typical-case errors yields general-purpose principles which are potentiall y helpful guidelines for users and architects. (C) 2001 IMACS. Published by Elsevier Science B.V. All rights reserved.