PartGen: A generator of very large circuits to benchmark the partitioning of FPGAs

This paper describes a new procedure for generating very large realistic be nchmark circuits which are especially suited for the performance evaluation of field-programmable gate array partitioning algorithms. These benchmark circuits can be generated quickly. The generation of a netlist of 100K conf igurable logic blocks (500K equivalent gates), for instance, takes only 2 m in on a standard UNIX workstation. The analysis of a large number of netlis ts from real designs lead us to identify the following five different kinds of subblocks: Regular combinational logic, irregular combinational logic, combinational and sequential logic, memory blocks, and interconnections. Th erefore, our generator integrates a subgenerator for each of these types of netlist, The comparison of the partitioning results of industrial netlists with those obtained from generated netlists of the same size shows that th e generated netlists behave similarly to the originals in terms of average filling rate and average pin utilization.