M. Zhao et Ss. Sapatnekar, Timing-driven partitioning and timing optimization of mixed static-domino implementations, IEEE COMP A, 19(11), 2000, pp. 1322-1336
Citations number
27
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Domino logic is a circuit family that is well-suited to implementing high-s
peed circuits. Synthesis of domino circuits is more complex than static log
ic synthesis due to the noninverting nature of the logic and the complex ti
ming relationships associated with the clock scheme, In this paper, we addr
ess several problems along a domino synthesis flow. We mainly consider the
problem of partitioning a circuit into static and domino regions under timi
ng constraints. The algorithm is extended to develop a method for partition
ing domino logic into two phases, with inverters permitted between the two
phases, and then to a flow for general two-phase static-domino partitioning
. We also address a timing verification and sizing optimization tool for ci
rcuits containing mixed domino and static logic.