Testing and testable designs for one-time programmable FPGAs

We present a methodology for production-time testing of one-time programmab le field programmable gate arrays (FPGAs) such as those manufactured by Act el [1]. The methodological principles are based on connecting the uncommitt ed modules (sequential and combinational logic circuits) of the FPGA as a s et of disjoint one-dimensional arrays, similar to iterative logic arrays (I LAs). These arrays can then be tested by establishing appropriate condition s for constant testability (C testability). Two design approaches are propo sed. Features such as testing time and hardware requirements (measured by t he number of cycles and additional transistors and primary input-output pin s) are analyzed. We show that the proposed designs require considerably les s testing time than a previous technique based on scan. The proposed approa ches require 8 + n(f) vectors for testing the FPGAs of [1], where n(f) is t he number of flip-flops in a row. Hardware overhead for the testing circuit ry is also analyzed.