Low-power weighted random pattern testing

Oftentimes, the power dissipation during the test mode far exceeds the powe r ratings of the normal operation mode. Hence, there is a need to reduce po wer during the test mode so that power ratings are not violated and chips d o not get burnt during the application of test. Power consumption during bu ilt-in-self-test (BIST) operation can be minimized while achieving high fau lt coverage. Simple measures of observability and controllability of circui t nodes are proposed based on primary input signal probability (probability that a signal is logic ONE). Such measures help determine the testability of a circuit. We developed a tool, POWERTEST, which uses a genetic algorith m based search to determine optimal probability sets (signal probabilities or input signal distribution) at primary inputs to tradeoff test time versu s power dissipation and fault coverage. The inputs conforming to the primar y input probability-activity sets can be generated using cellular automata or linear feedback shift register (LFSR). We observed that a single input d istribution (or weights) may not be sufficient for some random-pattern resi stant circuits, while multiple distributions consume larger area. As a trad eoff, two distributions have been used in our analysis. Results on ISCAS be nchmark circuits show that power reduction of up to 94.86% and energy reduc tion of up to 99.93% can be achieved (compared to equi-probable random-patt ern testing) while achieving high fault coverage.