Effect of parameter variations at chip and wafer level on clock skews

In this paper, a methodology is proposed to determine clock skews and the p erformance of clock architectures considering parameter variations in an ea rly stage of technology development. With this methodology, it is possible to separate process-induced clock ske w from other effects like imperfect loading. Parameter variations are seen as one of the most important effects influencing chip performance in future . By comparing a 0.45- and a 0.25-mum technology, it is shown that in the f uture, process variations will increase clock skew. The clock skews are det ermined by measuring the relevant device and metal line parameters as a fun ction of position over chip and wafer. In the past, parameters like IDS, Vt h, and resistances could be measured very precisely, although it was diffic ult to measure low capacitances of single metal lines in the range of femto farad. Thus a new measurement method is used to determine interconnect cap acitances extremely precisely. Based on these measurement data, a netlist of a defined clocktree is create d by a C-program, and the clock signal delay is simulated. From the delay s imulation, we calculate the clock skew for each chip dependent on the param eter variations. Experimental results are separated into a basic random flu ctuation part and processing-related contributions on the chip and wafer le vels. In addition, the effect of temperature gradients on each chip to the clock skew is simulated. The methodology presented is not restricted to just one clock tree but allo ws investigation of all kinds of clock distribution circuits. The method ha s clear advantages with respect to chip area against clocktree realizations on a testchip. No direct and costy measurement of signal delays by voltage contrast methods [1] is required, since all parameters are determined by m easurement on the device level.