Derivation of a nonlinear variance equation and its application to SOI technology

An analytic nonlinear equation for variance was derived along with a method based on response surface mapping techniques to calculate the variance usi ng the proposed equation. The technique was applied to the threshold voltag e of a 0.1-mum silicon-on-insulator MOS device, and the variance value obta ined was verified using Monte Carlo simulation. The threshold voltage depen dence upon active-layer thickness was found to be highly nonlinear due to t he device's going from the fully depleted to the partially depleted regime. Analysis of the variance showed that the effect of the nonlinear terms (18 .7%) is more important than the effect of the mixed term (-0.7%) and almost as important as the contribution of the second most dominant input-process parameter (23.6%). This illustrates the importance of the proposed nonline ar equation.