Experimental analysis and circuit model of an inductive type high temperature superconducting fault current limiter

A basic inductive type high temperature superconducting fault current limit er prototype has been built and tested at the Department of Electrical Engi neering of the University of Tokyo. The experimental static V-I characteris tics shows a change in the impedance of the device when its limiting curren t is reached. A circuit model of the fault current limiter is developed by means of a non linear inductor with memory. A good agreement is obtained be tween numerical and experimental V-I characteristics. Dynamic characteristi cs are numerically studied by means of the circuit model.