A switched priority scheduling mechanism for ATM switches with multi-classoutput buffers

In this paper, we propose a switched priority scheduling mechanism for an A synchronous Transfer Mode (ATM) switch with multi-class output buffers. The switched priority scheduling mechanism is composed of a model-based linear controller, a heuristic nonlinear controller and the corresponding switchi ng law of the controllers. The nonlinear controller is first applied to bri ng each class buffer into a small neighborhood of its operating point such that the linear controller can be used. The linear controller is then used to ensure that each buffer occupancy converges to its desired operating poi nt. The service rate of each class buffer is periodically computed and dyna mically adjusted. We derive the design formulae of the control mechanism su ch that each buffer occupancy globally converges to its desired operating p oint related to quality-of-service requirements. (C) 2001 Elsevier Science B.V. All rights reserved.