An on-chip ESD protection circuit with low trigger voltage in BICMOS technology

A novel low-trigger dual-direction on-chip electrostatic discharge (ESD) pr otection circuit is designed to protect integrated circuits (ICs) against E SD surges in two opposite directions. The compact ESD protection circuit fe atures low triggering voltage (similar to7.5 V), short response time (0.18- 0.4 ns), symmetric deep-snap-back I-V characteristics, and low on-resistanc e (Nn). It passed the I l-kv human body model (HBM) ESD test and is very ar ea efficient ( similar to 80 V/mum width). The new ESD protection design is particularly suitable for low-voltage or multiple-power-supply IC chips.