Resynchronization for multiprocessor DSP systems

This paper introduces a technique, called resynchronization, for reducing s ynchronization overhead in multiprocessor implementations of digital signal processing (DSP) systems. The technique applies to arbitrary collections o f dedicated, programmable or configurable processors, such as combinations of programmable DSP's, ASICS, and FPGA subsystems. Thus, it is particularly well-suited to the evolving trend toward heterogeneous single-chip multipr ocessors in DSP systems. Resynchronization exploits the well-known observat ion [43] that in a given multiprocessor implementation, certain synchroniza tion operations may be redundant in the sense that their associated sequenc ing requirements are ensured by other synchronizations in the system. The g oal of resynchronization is to introduce new synchronizations in such a way that the number of original synchronizations that become redundant exceeds the number of new synchronizations that are added, and thus, the net synch ronization cost is reduced. Our study is based in the context of self-timed execution for iterative dat aflow specifications of DSP applications. An iterative dataflow specificati on consists of a dataflow representation of the body of a loop that is to b e iterated indefinitely; dataflow programming in this form has been employe d extensively in the DSP domain.