Scheduling with bus access optimization for distributed embedded systems

In this paper, we concentrate on aspects related to the synthesis of distri buted embedded systems consisting of programmable processors and applicatio n-specific hardware components. The approach is based on an abstract graph representation that captures, at process level, both dataflow and the flow of control, Our goal is to derive a worst case delay by which the system co mpletes execution, such that this delay is as small as possible; to generat e a logically and temporally deterministic schedule; and to optimize parame ters of the communication protocol such that this delay is guaranteed. We h ave further investigated the impact of particular communication infrastruct ures and protocols on the overall performance and, specially, how the requi rements of such an infrastructure have to be considered for process and com munication scheduling. Not only do particularities of the underlying archit ecture have to be considered during scheduling but also the parameters of t he communication protocol should be adapted to fit the particular embedded application, The optimization algorithm, which implies both process schedul ing and optimization of the parameters related to the communication protoco l, generates an efficient bus access scheme as well as the schedule tables for activation of processes and communications.