Partitioning sequential circuits for pseudoexhaustive testing

In this paper, we present an algorithm for partitioning sequential circuits . This algorithm is based on an analysis of a circuit's primary input cones and fanout values (PIFAN), and it uses a directed acyclic graph to represe nt the circuit. An invasive approach is employed, which creates logical and physical partitions by automatically inserting reconfigurable test cells a nd multiplexers. The test cells are used to control and observe multiple pa rtitioning points, while the multiplexers expand the controllability and ob servability provided by the test cells. The feasibility and efficiency of o ur algorithm are evaluated by partitioning numerous standard digital circui ts, including some large benchmark circuits containing up to 5597 gates. Ou r algorithm is based upon pseudoexhaustive testing methods where fault simu lation is not required for test-pattern generation and grading; hence, engi neering design time and cost are further reduced.