Synthesis for logical initializability of synchronous finite-slate machines

Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, X) simulator, In practice, commercial logic and fault simulators often require initialization under such a three-valued simulation model. In this paper, the first sound and systematic synthesis method is proposed to ensur e the logical initializability of synchronous finite-state machines. The me thod includes both state assignment and combinational logic synthesis steps . It is shown that a previous approach to synthesis-for-initializability, w hich uses a constrained state assignment method, may produce uninitializabl e circuits. Here, a new state assignment method is proposed that is guarant eed correct. Furthermore, it is shown that combinational logic synthesis al so has a direct impact on initializability; necessary and sufficient constr aints on combinational logic synthesis are proposed to guarantee that the r esulting gate-level circuits are logically initializable, The above two syn thesis steps have been incorporated into a computer-aided design tool, sals ify, targeted to both two-level and multilevel implementations.