Threshold logic circuit design of parallel adders using resonant tunnelingdevices

Resonant tunneling devices and circuit architectures based on monostable-bi stable transition logic elements (MO-BILEs) are promising candidates for fu ture nanoscale integration. In this paper, the design of clocked MOBILE-typ e threshold logic gates and their application to arithmetic circuit compone nts is investigated. The gates are composed of monolithically integrated re sonant tunneling diodes and heterostructure field-effect transistors. Exper imental results are presented for a programmable NAND/NOR gate, Design rela ted aspects such as the impact of lateral device scaling on the circuit per formance and a bit-level pipelined operation using a four phase clocking sc heme are discussed. The increased computational functionality of threshold logic gates is exploited in two full adder designs having a minimal logic d epth of two circuit stages. Due to the self-latching behavior the adder des igns are ideally suited for an application in a bit-level pipelined ripple carry adder. To improve the speed a novel pipelined carry lookahead additio n scheme for this logic family is proposed.