Interfacing synchronous and asynchronous modules within a high-speed pipeline

This paper describes a new technique for integrating asynchronous modules w ithin a high-speed synchronous pipeline. Our design eliminates potential me tastability problems by using a clock generated by a stoppable ring oscilla tor, which is capable of driving the large clock load found in present day microprocessors. Using the ATACS design tool, we designed highly optimized transistor-level circuits to control the ring oscillator and generate the c lock and handshake signals with minimal overhead. Our interface architectur e requires no redesign of the synchronous circuitry. Incorporating asynchro nous modules in a high-speed pipeline improves performance by exploiting da ta-dependent delay variations, Since the speed of the synchronous circuitry tracks the speed of the ring oscillator under different processes, tempera tures, and voltages, the entire chip operates at the speed dictated by the current operating conditions, rather than being governed by the worst case conditions. These two factors together can lead to a significant improvemen t in average-case performance, The interface design is simulated using the 0.6-mum HP CMOS14B process in HOSPICE.