Area-time-power tradeoff in cellular arrays VLSI implementations

Designing pipelined cellular arrays for arithmetical purposes, the choice o f circuit design style is crucial. Usually, this choice is made by establis hing an optimal area-time-power tradeoff. In order to achieve this result, analysis and simulations of the whole designed array have to be repeatedly performed for several design styles, This paper presents a methodology that allows the same result to be obtained avoiding time-consuming simulations of an entire array. The proposed technique is based on an appropriate parti tioning of the arrays into small subcircuits. The features of the latter ar e analytically recomposed to evaluate performances and costs of an array of any size for various design approaches.