Low-stress hybridisation of emitters, detectors and driver circuitry on a silicon motherboard for optoelectronic interconnect architecture

In the absence of a truly integrated silicon optoelectronics technology, ma nufacturable hybridisation technologies for III-V optoelectronic components , compatible with silicon and CMOS substrates, are essential for optoelectr onic interconnect. The hybridisation technology for a clock distribution op tical interconnect architecture is reported. A substrate removal technology for an 8 x 8 array of 10 mum thick VCSEL coupons is described, and the per formance of AlAs and AlGaAs etch stop layers is discussed. Optoelectronic s ystems which depend on the retention of the polarisation specific nature of components restrict the mechanical constraints on their manipulation and b onding, to avoid stresses which could destroy the polarisation specificity of the component. A low-stress pick and place technology using a mask align er has been employed. Eight hundred and fifty nanometres top-surface emitti ng GaAs/AlGaAs VCSELs, InGaAs/InP p-i-n photodiode arrays, and high-frequen cy CMOS silicon driver chips have been hybridised on silicon motherboards u sing this technology. The factors influencing the choice of bonding materia ls and the sequence of component hybridisation, including the requirements of subsequent planarisation and wiring processes, are discussed. The source s of alignment error are reported. Examples of working emitters, detectors and driver circuitry hybridised using this technology are presented. (C) 20 01 Elsevier Science Ltd. All rights reserved.