HIERARCHICAL DELAY TEST-GENERATION

Delay testing is used to detect timing errors in a digital circuit. In this paper, we report a tool called MODET for automatic test generati on for path delay faults in modular combinational circuits. Our techni que uses precomputed robust delay tests for individual modules to comp ute robust delay tests for the module-level circuit. We present a long est path theorem at the module level of abstraction which specifies th e requirements for path selection during delay testing. Based on this theorem, we propose a path selection procedure in module-level circuit s and report efficient algorithms for delay test generation. MODET has been tested against a number of hierarchical circuits with impressive speedups in relation to gate-level test generation.