An effective model to evaluate the leakage currents for different stacked g
ates deep submicron MOS transistors is presented. For a given equivalent ox
ide thickness of a stacked gate, the gate leakage current decreases with an
increase of high-k dielectric thickness or a decrease of interlayer thickn
ess. Turning points at high gate biases of the I-V curves are observed for
Si3N4SiO2, Ta2O5/SiO2, Ta2O5/SiO2-yNy, Ta2O5/Si3N4, and TiO2/SiO2 stacked g
ates except for Al2O3/SiO2 structure, Design optimization fur the stacked g
ate architecture to obtain the minimum gate leakage current is evaluated. (
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