Self-aligned silicon-on-insulator nano flash memory device

This paper reports on the fabrication of a silicon-on-insulator nano flash memory device based on the differential oxidation rate of silicon resulting from gradients in the arsenic doping concentration. The key processes invo lved are the formation of the desired arsenic doping profile, electron beam lithography and wet oxidation. The resulting device is a triangular-channe l MOSFET with a nanocrystal floating gate embedded in the gate oxide. The l ength, width and height of the nanocrystal are 10, 10 and 20 nm, respective ly. As long as the control gate voltage does not exceed +/-2V, the device b ehaves like a thin and narrow P-channel MOSFET. When a voltage of -5 or +5 V is applied to the control gate at room temperature, holes are injected in to the floating gate or removed from it, respectively. This effect induces a persistent shift of the threshold voltage of the device, which acts as a miniature EEPROM. (C) 2000 Elsevier Science Ltd. All rights reserved.