High-performance VLSI architecture of multiplierless LMS adaptive filters using distributed arithmetic

Currently, considerable research is being performed on multiplierless struc tural methods for fixed coefficient filters, but not much research has been done on structural methods for creating adaptive filters whose coefficient s vary with time. A few multiplierless structural methods have been propose d as structural methods using distributed arithmetic, but these conventiona l methods use particular encoding for input signals, and thus experience ve ry high levels of degradation in their convergence characteristics. The aut hors improve significantly the convergence characteristics by generalizing this method using a new two's complement method. In addition, the authors p ropose a VLSI architecture not considered in conventional methods and perfo rm VLSI evaluations of their structural method. The results show that the a uthors' proposed method can dramatically reduce power consumption and hardw are requirements while sustaining high performance and very low latency com pared to structural methods that use a multiplier. (C) 2001 Scripta Technic a.